`timescale 10ns / 10ns

module key_buzzer_top_tb;

    reg clk, rst_n, key;
    wire buzzer;

    initial begin
        $dumpfile("output/key_buzzer_top_tb.vcd");
        $dumpvars(0, key_buzzer_top_tb);
    end

    initial begin
        clk = 0;
        rst_n = 0;
        #10 rst_n = 1;
        #10 key = 0;
        #2000_000;
        #10 key = 1;
        #2000_000;
        #10 key = 0;
        #2000_000;
        #10 key = 1;
        #2000_000;
        #1000 $stop;
    end

    always #1 clk = ~clk;

    key_buzzer_top key_buzzer_top_inst (
        .clk_50m                (clk),
        .rst_n                  (rst_n),
        .key                    (key),
        .buzzer                 (buzzer)
    );

endmodule